Integrated circuits (IC) may be used in a wide range of designs and products, some integrated circuits may include Non-Volatile Memory (NVM) arrays. An NVM array may be composed of NVM cells, ancillary circuitry, a controller and additional circuits. The ancillary circuitry may include for example: array controls, address decoding circuits and sense amplifiers (SA) and/or comparators. SAs may be configured to determine a value/level of one or more targeted NVM cell.
Some memory array types may include NVM arrays, floating gate arrays, array of eCT cells, array of MirrorBit cells, charge trapping cells and more.
The NVM cells may be single bit or multi-level storage cells, and the cells may be programmable to different states. For example, in a single bit configuration the cell may be programmable to either an erased (ERS) or programmed (PRG) state.
According to some embodiments, the NVM cells may be accessed internally in the IC through wordlines (WLs), bitlines (BLs), select lines (SLs), memory gates (MGs) or otherwise. For each sequence (Programming of cells, Erasing of cells, Reading of cells etc.), the WLs, BLs, SLs, and/or MGs may be activated accordingly. Operating mode, such as read algorithm, program algorithm, erase algorithm, may determine voltage or current signals applied to WLs, SLs, SGs, MGs of NVM cells. Other factors include the selected addresses, the specific technology being used. In some embodiments, the NVM arrays may include different structural features and may not include select gates (SGs), BLs, SLs, MGs and/or WLs, or otherwise.
Some transistor types which may be used in associated circuitry are Pmos, Nmos, low voltage (LV) Nmos, LV Pmos, high voltage (HV) Nmos and HV Pmos, Zmos which is a low resistance Nmos or Pmos transistor, bipolar junction transistor (BJT), and more. HV transistors/cells may be differentiated from LV transistors/cells by being designed/configured to enable operation in a higher range of voltages across their channel compared to LV cells (for example, between a drain node and a source node of the transistor) and/or across the gate (for example: between their gate and bulk or ground node), and may include a thick oxide region compared to LV devices.
Externally, a host device may including an IC and/or a memory array which may be accessed by a user/host device by sending a user/host device command to carry out a User Read operation, User Program operation, User Erase Operation or otherwise and may include an address that is requested to have the operation applied to. In response to the user Read command, information from the memory device may be output to the user/host device. In response to a User Program command, information may be stored in the memory device. In response to a User Erase command, a segment of the memory may be erased.